IEEE Boundary Scan Architecture and Boundary Cell Selection Basics
Selecting boundary cells matching pin drive requirements enables full interconnect fault coverage and prevents system logic corruption during shift sequences.
BC_2 Cell
Signal Capture
Boundary scan architecture components designed for bidirectional pins allow for the observation of internal logic states and the control of physical output drivers. The bc_2 cell provides a standardized mechanism for digital test patterns to interface with integrated circuit pins during board level continuity checks. It resides between the core logic and the physical bond pad.
Output Control
Output control via this specific cell type involves a multiplexer that selects between the functional core logic and the test data stored in the shift register. When the device enters an external test mode, the bc_2 cell forces a known logic level onto the board trace to verify the integrity of the interconnect. This allows an automated tester to confirm that the receiving pin on another component sees the correct transition.
Bidirectional Logic
Bidirectional logic requires two of these cells working in tandem with a third cell to manage the three state enable line of the driver. One bc_2 cell handles the data being driven out of the chip while another captures the data arriving from the board. This configuration allows a test engineer to verify both the output capability of the pin and the input sensing circuitry.
Because the architecture lacks an input latch, it remains simpler and smaller than more complex cell designs found in high performance boundary scan implementations.