Plating Equalization
Non-functional copper shapes added to the unused areas of a printed circuit board panel distribute the electrical current evenly during the electroplating process. Known as current density thieving, this design technique prevents excessive copper buildup on isolated traces on the panel margins. By providing a balanced surface area of conductive metal across the panel, the electroplating bath deposits metal at a uniform rate.
This prevents high-current nodes from drawing too much metal and forming thick, out-of-spec traces.
Fabrication Setup
Distributing sacrificial copper patterns, often as grids of small squares or dots, onto the outer borders of the panel balances the electrical load. Isolated traces without these neighboring shapes would receive a disproportionately high current density, leading to plating burn or excessive height. Fabricators use specialized computer-aided manufacturing software to calculate the optimal location and density of these thieving patterns.
This automated addition ensures that the copper thickness remains uniform across both high-density and low-density routing regions of the panel.
Impedance Control
Uniform trace thickness is critical for maintaining consistent signal impedance across all high-speed lines. When traces are plated too thick due to localized high current, their cross-sectional area changes, which reduces their characteristic impedance. By applying current density thieving, the height of the copper traces is kept within tight tolerances, preserving the signal integrity of the high-speed routing.
