Voltage Margin
High-speed receiver circuits evaluate digital signal integrity by calculating the vertical voltage opening within a synchronized bit period. The metric known as eye height measures this vertical difference between logic high and logic low signal levels at the sampling point. Thermal noise and crosstalk from adjacent traces close this vertical opening during transmission across a circuit board.
A receiver fails to distinguish logic states when amplitude noise exceeds half of this vertical distance.
Attainable Opening
Lossy dielectric substrates attenuate high-frequency harmonics, rounding rectangular pulses into smoothed waveforms that reduce signal amplitude. When differential pairs traverse long routed paths on epoxy laminates, dielectric absorption and conductor skin effect attenuate signal peaks before reaching the receiver terminals. Signal integrity simulation tools calculate eye height from simulated pseudo-random bit sequences to verify receiver compliance before artwork release.
Automated oscilloscope software extracts this value by overlaying thousands of consecutive bit intervals into a composite persistence diagram. Standard compliance specifications establish minimum vertical clearance values in millivolts to guarantee low bit error rates across environmental operational limits. Manufacturing defects such as inconsistent trace width or poor etching profile induce impedance mismatches, creating reflections that erode voltage margins.
Acceptance Threshold
Physical testing verifies whether receiver equalization can restore compressed signals to specified limits. Continuous time linear equalization boosts high-frequency gain to counteract dielectric loss and expand vertical amplitude. When passive attenuation exceeds the equalization capacity of the silicon, bit error rates climb rapidly beyond allowable boundaries.
Automated optical and electrical compliance testing flags circuit assemblies that fail vertical opening requirements under worst-case jitter conditions. System reliability depends on maintaining positive vertical clearance across supply voltage variations and temperature shifts.
