Detection Statistics
Numerical values represent the mathematical ratio of physical defects identifiable by a test sequence relative to the total population of modeled failure modes. Fault coverage metrics provide the quantitative basis for validating the efficiency of automatic test equipment during printed circuit board assembly. Designers calculate these values by dividing the number of detectable faults by the total number of theoretical faults present in a netlist.
A higher percentage confirms that the programmed stimulus pattern effectively exercises the functional paths and solder connections across the hardware under review.
Diagnostic Precision
Verification engineers deploy these calculations to quantify how many unintended variations or latent manufacturing flaws remain hidden from a structural test suite. These computations allow teams to map the boundaries of test effectiveness before units move to physical production. Each calculation depends on the fidelity of the fault model, which might target stuck at conditions or bridge shorts between adjacent signal tracks.
Inadequate test patterns reveal low values, forcing engineers to add test points or implement boundary scan cells to improve visibility. Complex boards require sophisticated algorithmic analysis to ensure that every circuit node receives adequate excitation.
Boundary Limits
Mathematical boundaries define the maximum possible score achievable by any specific testing strategy on a given hardware configuration. These limits arise because certain components or signal architectures prevent complete physical access for probe or boundary scan testing. Physical constraints like dense ball grid array packaging or buried vias often prevent the total detection of every latent open circuit or short.
A perfect score rarely occurs in practice because the cost of reaching full observability exceeds the value gained from the incremental improvement in reliability. Absolute fault coverage metrics represent an ideal state that shifts whenever designers modify the circuit topology.