Standard Description
Standardization of access mechanisms for embedded instruments within semiconductor devices provides a uniform method to manage on chip test structures. The specification known as IEEE 1687 defines a description language and a hierarchical test access architecture to connect embedded monitors to the primary test interface. This framework allows engineers to configure and communicate with diverse internal monitors without designing custom test logic.
Dynamic Architecture
Dynamic control of the test scan path is achieved through gateway blocks that insert or remove shift register segments on demand. Instead of a fixed length scan chain that requires long clock sequences, IEEE 1687 allows the test processor to open or close bypass paths depending on which instruments are active. This mechanism optimizes test time by shortening the scan chain during board level diagnostic routines.
Scan description language is used to describe the connections, while procedural description language specifies the commands sent to the instruments.
Operational Advantage
Hardware testing at the board level becomes faster and more modular when chip level instruments are accessible through a uniform language. Test routines written during chip design are reused during board assembly verification, which reduces the effort needed to write boundary scan test vectors. This reuse translates to faster failure isolation on complex digital assemblies.
