Software Assessment
Verification of the electrical headroom in a functional computer system uses internal hardware registers to measure signal quality. Through lane margining, the system firmware or diagnostic software can sweep the voltage and timing offsets of a high speed bus while it is active. This process identifies how close the link is to failing without requiring external laboratory equipment.
Physical Layer
Testing occurs at the receiver by moving the sample point away from the center of the signal eye until errors begin to appear. The resulting data provides a real world view of the signal integrity after the board has been fully assembled and populated with components. This allows for the detection of issues that only appear during the high speed operation of the entire system.
Because it is performed in the field or during final factory test, it accounts for the actual temperature and power noise of the environment.
System Stability
Adoption of this protocol in standards like PCIe ensures that the link will remain stable over the life of the product. If the margining results are too low, the system can down train the link to a slower speed to prevent data corruption. It is a vital tool for validating the margin of safety in large scale server deployments.
