Electrical Susceptibility
The critical voltage or current limits define when a low-impedance path is triggered in a complementary metal-oxide-semiconductor integrated circuit. These limits, termed latch-up thresholds, are determined by the internal parasitic silicon-controlled rectifier structures formed by adjacent n-channel and p-channel transistors. Once triggered, the parasitic structure draws excessive current from the power supply, which can destroy the device.
Silicon manufacturers test these limits to guarantee that their components resist transient disturbances.
Protective Layout
Integrated circuit layout techniques minimize the gains of the parasitic transistors to prevent the activation of the low-impedance path. To increase latch-up thresholds, chip designers place guard rings between the p-wells and n-wells and reduce the substrate resistance. On the printed circuit board, transient voltage suppressors and decoupling capacitors prevent external voltage spikes from exceeding the input ratings of the chip.
These design practices ensure that the integrated circuit remains stable in noisy electrical environments. Adding series resistance to input pins also limits the injected current during a transient event, keeping the signal levels below the trigger point.
Verification Method
Standardised testing protocols apply electrical stresses to the pins of the device to determine the point of failure. Testing for latch-up thresholds involves injecting current pulses into the input and output pins or overvoltage pulses onto the power supply rails. The test confirms that the device remains within functional limits without drawing excessive current.
