Verification of Thermal Rework Degradation Limits for Multi-Layer Board Assemblies
Verification of thermal rework degradation limits relies on coupon continuous resistance tracking and microsectioning to prevent latent inner-layer via cracking.
Microsectioning Protocol
Destructive Inspection
Systematic procedures for cutting, mounting, grinding and polishing a circuit board sample provide a cross-sectional view of internal structures. A microsectioning protocol ensures that the preparation process does not introduce artifacts like cracks or smears that might be mistaken for defects. This test is the primary way to verify the quality of plated through holes and internal layer alignments.
Preparation Steps
Technicians first cut a small coupon from the board and encapsulate it in a hard resin. Once the resin cures, the sample undergoes several stages of grinding with increasingly fine abrasive paper. Water or oil lubricants prevent the sample from overheating during the grinding process.
The final step involves polishing with a diamond or alumina slurry to achieve a mirror-like finish. This smooth surface allows for the clear identification of intermetallic layers and plating thicknesses under a microscope. Each step must be completed carefully to avoid pulling copper away from the hole walls.
Visual Verification
Microscopic examination of the finished section reveals the true state of the internal connections. Measurement of the copper plating at the thinnest point of the barrel confirms compliance with manufacturing specifications. This inspection catches errors that electrical testing cannot detect.