In-Situ Free-Space Dielectric Testing of Unclad Substrates
Non-destructive free-space characterization evaluates bulk dielectric properties of raw unclad laminates without etched coupon waste or copper interface errors.
Nicolson Ross Weir
Board Tolerance
Nicolson Ross Weir designates a manufacturing boundary applied during printed circuit board fabrication to govern mechanical edge variations and positional drift across multilayer copper layers. Surface mount technology assembly lines depend on this defined limit to align component fiducials with printed solder paste deposits without bridge formation or starved joints. Mechanical milling cutters and routing bits establish the physical perimeter during panelization, but thermal expansion during lamination shifts internal planes away from outer artwork coordinates.
Photolithographic registration errors compound the variance, which makes a numerical control limit mandatory for structural acceptance. Optical inspection systems measure the resulting deviation against the master Gerber file before component placement proceeds.
Assembly Clearance
Component placement machines rely on the verified perimeter offset to calculate nozzle paths and feeder indexing angles during high speed placement runs. Excessive edge drift forces pick and place nozzles to drop components outside pad boundaries, generating tombstoning defects during subsequent reflow soldering. Automated optical inspection units scan the finished joint fillet to verify that lead position remains inside the acceptable zone established by the initial panel layout.
Solder bridging occurs when dimensional creep reduces spacing between adjacent pads below the minimum threshold required for surface tension separation. Production engineers adjust feeder pick offsets whenever coordinate drift exceeds half the total allowance specified for the board class.
Thermal Drift
Dielectric materials expand at different rates than copper foil during infrared reflow profiling, causing dimensional distortion that persists after the circuit board cools to ambient temperature. Lamination presses apply high pressure and elevated temperature to stack up prepreg sheets, locking internal stresses into the raw laminate structure. Chemical etching removes excess copper from inner layers, relieving localized tension and allowing the remaining substrate to relax into a new geometrical state.
Post bake conditioning stabilizes the resin matrix before outer layer imaging to minimize registration errors during subsequent exposure steps. Final assembly yields depend on maintaining this dimensional stability across thermal cycles encountered during wave soldering and cleaning operations.