Electrical Impedance
Unintended self-inductance is introduced by the fine wire connections that run between an integrated circuit die and the package leadframe. This physical property, known as parasitic bond wire inductance, opposes changes in high-frequency current and generates voltage drops across the connection. In high-speed digital circuits, this inductance causes ground bounce and signal degradation.
Managing this effect is critical for preserving signal integrity at high frequencies.
Package Design
Packaging technologies reduce the length and number of bond wires to minimize their electrical effects on high-frequency signals. To mitigate parasitic bond wire inductance, component manufacturers use multiple parallel bond wires or transition to flip-chip packaging where solder bumps replace wires. Shorter connections decrease the inductive loop area and lower the impedance.
These design changes improve the high-frequency performance of the integrated circuit within its assembly. In addition, using wider copper ribbons instead of thin gold wires reduces the overall inductance and improves power delivery.
Assembly Inspection
High-magnification inspection and electrical characterisation confirm that bond wire geometry and length meet specification limits. Excessively long or looping wires increase parasitic bond wire inductance and are detected during package assembly using optical or x-ray systems. Ensuring consistent wire heights helps maintain predictable impedance values across different production batches.
