Test Constraint
Electrical testing of bare boards relies on physical contact between test probes and designated test points to verify electrical continuity. The unprobed netlist limits represent the nets or nodes within a circuit design that cannot be accessed by the test equipment. These untested traces escape electrical verification, creating a risk that latent shorts or opens remain undetected.
Designers strive to minimize these limits by adding test points to every net.
Physical Access
Physical access is restricted by high-density layouts and fine-pitch components that do not have enough space for dedicated test pads. Modern designs with microvias and buried traces often hide entire nets within the internal layers of the board. Flying probe testers require a minimum pad size and spacing to avoid damaging the board or colliding with other probes.
When these physical limits are reached, the test coverage decreases, forcing manufacturers to rely on other inspection methods.
Risk Mitigation
To compensate for these limits, manufacturers use automated optical inspection and automated x-ray inspection to check the solder joints of unprobed nets. These non-contact methods verify the physical integrity of the connections, which reduces the escape rate of assembly defects. While these visual checks are helpful, they cannot guarantee electrical performance.