Outer Boundary
Copper ring geometry loss where annular spacing around a plated through hole transitions outward during photolithography etching is measured by via capture pad breakout. Fabrication lines control registration tolerances across both panel sides to prevent mechanical weakness during subsequent soldering stages. Etching solutions dissolve excess metal past the designed annular ring when photoresist alignment drifts beyond acceptable limits.
Automated optical inspection equipment flags this copper reduction before boards reach component placement lines. Inner layer misalignment generates similar copper reduction during multi layer pressing cycles. Subsequent thermal stress during wave soldering exacerbates marginal connections left by reduced copper annular rings.
Structural Limit
Annular ring reduction compromises electrical continuity once drilling tolerances exceed available copper boundaries on internal signal planes. Mechanical stress from thermal expansion during surface mount reflow breaks weakened copper connections at barrel interfaces. Circuit board assemblers test finished assemblies using in circuit electrical probes to detect open circuits caused by extreme annular ring loss.
Designers specify minimum annular ring widths to withstand the rigors of mechanical drilling tolerances without inducing functional failures. Manufacturing engineers adjust drill speeds to minimize copper tearing around the periphery of the hole.
Process Verification
Microsection analysis provides destructive cross sectional verification of internal copper rings relative to drilled barrel walls. Quality laboratories grind through plated through holes horizontally to measure remaining copper dimensions under magnification. Optical measurement software calculates the percentage of copper remaining on each side of the barrel.
Automated X ray inspection systems evaluate inner layer registration non destructively on multi layer panels prior to lamination. Component placement facilities reject panels exhibiting insufficient copper retention before populating expensive semiconductor packages onto the surface.
