Impedance Peak
Parallel resonance in a power distribution network creates a localized frequency node where capacitive and inductive reactances cancel each other out. Operating conditions near antiresonance generate substantial voltage ripple across power planes, driving board impedance above specified target thresholds. The condition occurs when discrete decoupling capacitors interact with board plane capacitance or parasitic trace inductance.
Peak amplitude depends on the equivalent series resistance of the component array.
Circuit Mechanism
Component placement and dielectric thickness establish the physical loop inductance that dictates where parallel resonance occurs. When an integrated circuit draws transient current at the parallel resonant frequency, the power delivery network exhibits high impedance rather than low impedance. Antiresonance converts switching currents into voltage fluctuations that propagate across the printed circuit board, causing signal integrity degradation or logic errors.
Higher loss factors in dielectric materials attenuate the peak height, whereas ultra-low equivalent series resistance capacitors sharpen the resonance spike. Design engineers simulate the total impedance spectrum across the operating band from direct current to several gigahertz to identify problematic peaks before board fabrication. Board layout geometry modifies loop area, shifting the resonant point across the frequency spectrum.
Mitigation Strategy
Strategic staggering of capacitor values distributes resonant frequencies across a broader spectrum to suppress individual impedance spikes. Combining different package sizes breaks up constructive current addition. Damping resistors placed in series with specific capacitors lower the peak amplitude without degrading low-frequency decoupling performance.
Targeted plane sizing suppresses high frequency antiresonance spikes across power delivery networks.