Screening Methodology
An environmental testing method applies simultaneous electrical voltage and thermal stress to printed circuit board assemblies to accelerate the onset of latent workmanship defects before field deployment. In typical manufacturing runs, bias stress screening exposes these assemblies to cyclic temperature transitions while electrical loads run through the circuitry. This action precipitates infant mortality failures without aging the robust assemblies.
Stress Driver
Voltage and temperature act as the primary drivers of degradation during these screening procedures. Solid-state devices and multi-layer board structures respond to the combined thermal-electrical load by undergoing accelerated kinetic reactions. The acceleration follows the Arrhenius equation for thermal effects alongside voltage acceleration models to predict the rate of degradation.
Technicians monitor the current drawn by the board during the test to detect sudden shifts that indicate dielectric breakdown or internal short circuits. This active monitoring distinguishes the screening from passive thermal baking where assemblies are simply heated without electrical activation. Because bias stress screening uses continuous electrical paths, it captures intermittent faults that disappear once the assembly cools to room temperature.
Acceptance Limit
Reliability parameters dictate the duration and intensity of the applied electrical and thermal loads to ensure the test does not consume too much of the remaining lifetime of the assembly. A prolonged exposure to elevated stress or excessive voltage sweeps can degrade healthy polymer substrates and weaken copper interconnects. Manufacturers establish specific stress ceilings that trigger immediate termination of the cycle if current spikes occur.
The test cycle completes successfully when the assembly maintains its specified electrical performance throughout the entire duration of the thermal profile.