Boundary Scan Integration for High Density Circuit Assemblies
Boundary scan integration replaces physical test points with silicon registers, securing structural fault coverage on high density circuit assemblies.
Boundary Scan Register
Internal Architecture
Specialized shift register chains embedded within boundary-scan-compliant integrated circuits enable the control and observation of the device pins. In a boundary scan register, individual memory cells are placed between the internal logic of the chip and each physical input or output pin. This sequential arrangement allows the test system to isolate the component pins for testing or programming purposes without requiring physical probe access.
Data Flow
Operation of these register cells involves shifting serial data through the test access port using the standard test data input and test data output lines. When the device is put into a test mode, the boundary scan register can latch signals from the input pins or drive specific logic states onto the output pins. This register-shifting process is controlled by a state machine that transitions based on the clock signal applied to the test clock pin.
Solder joints are tested for open circuits or short circuits by shifting test patterns into the output registers of one chip and shifting them out of the input registers of another.
Scan Limitation
While this integrated register provides excellent digital observability, it cannot directly measure analog voltages or high-frequency characteristics of the lines. It relies on the presence of functional boundary-scan-compatible devices at both ends of the trace to achieve full diagnosis.