Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Vectors
Automatic pattern generation translates design netlists into binary pin stimuli executed across boundary-scan architecture. Board test routines isolate individual electrical nodes to assess copper traces across internal and external layers. Because opens and unintended solder bridges change node impedance and signal transmission, structural vector sets toggle boundary registers to catch these defects before functional power-up.
Structural Fault Models and Pattern Algorithmics
Interconnect fault models target physical defects along board traces and component leads. Stuck-at-0 and stuck-at-1 conditions model hard shorts to ground or power planes. Open faults represent broken signal paths, whether from missing solder joints, lifted pins, cracked microvias, or fractured copper traces.
Bridging faults model low-resistance shorts between adjacent nets caused by solder bridging, copper whiskers, or conductive debris.
How bridging faults behave depends on the driver logic family and board design. Wired-AND behavior pulls shorted nets low whenever any driver outputs a logic low, while wired-OR pulls them high if any driver goes high. Dominant and anti-dominant faults occur when one output driver overrides its neighbours regardless of state.
Pattern algorithms must therefore generate vector structures that match these specific electrical interactions.
Algorithms for automatic pattern generation diverge significantly in runtime, memory demand, and diagnostic accuracy. Walking 1s and Walking 0s routines apply an active logic state to a single net while holding all remaining nets at the complementary level. Vector depth scales linearly with net count: a design with one thousand nets requires one thousand vector cycles.
While execution time climbs steadily, the diagnostic resolution isolates shorted net pairs without ambiguity.
Logarithmic algorithms compress test times by driving binary counting sequences across net groups. Wagner sequences assign binary values matching each net index, allowing pattern depth to scale with the ceiling of log base two of net count plus two cycles. Driving simple binary counts risks aliasing, where shorted nets generate identical combined signatures, or shadow faults, where one short conceals an open behind it.
Modified counting sequences resolve aliasing by generating true and complement bit pairs back-to-back, guaranteeing unique vector signatures across all nets.
| Algorithm Type | Vector Growth Complexity | Target Fault Universe | Undetected Defect Modes | Diagnostic Resolution |
|---|---|---|---|---|
| Walking One and Zero | Linear O(N) | Single Stuck-At, Opens, 2-Pin Shorts | High-Order Multi-Pin Shorts | Pin Level Precision |
| Wagner Counting Sequence | Logarithmic O(log2 N) | Single Stuck-At, Multi-Pin Shorts | Aliasing and Shadow Shorts | Net Group Resolution |
| Modified Counting Sequence | Logarithmic O(2 log2 N) | Stuck-At, Opens, Bridging Shorts | AC Coupled Differential Opens | Individual Net Resolution |
| True Complement Vectoring | Logarithmic O(2 log2 N + 2) | DC Interconnect Shorts and Stuck-At | High Impedance Parametric Leakage | Pin Pair Precision |
Counting Sequences and Contention Avoidance
Exciting drivers in parallel catches bridging shorts quickly, but driving opposing logic states simultaneously across shared buses draws excessive current through output transistors. Automatic pattern generators evaluate boundary scan control cells to manage tri-state output buffers, holding inactive drivers on shared buses in high-impedance states during individual net excitation steps.
Contention routines parse netlists for multi-driver buses, bidirectional pins, and wired logic nodes. Compiler engines insert dedicated setup vectors to disable unselected drivers before test patterns fire, and true-complement routines add bus hold delays to confirm that buffers have fully released. Without strict control over driver states, transient current spikes can stress silicon and trigger false failure calls.
Running basic counting sequences without modified complement vectors leaves undetected shorts across adjacent dense bus lines, pushing diagnostic costs directly into downstream functional test.
Probe
Boundary scan replaces traditional bed-of-nails test fixtures by integrating test cells directly into active silicon. High component density on modern assemblies leaves little room for physical test pads, and ball grid array packages conceal their solder joints underneath the component body. Boundary scan architecture sidesteps physical access limits by moving pin stimulus and response monitoring into the IC itself.
Boundary Cell Architecture and Scan Access Limits
Shift registers, update latches, and multiplexers sit directly between the component’s internal logic and its package pins. Driven by test clock and test mode select lines, the test access port controller cycles through its sixteen-state finite state machine, clocking serial data in through test data in and out through test data out. During interconnect checks, boundary scan cells capture pin states, shift vector patterns along the scan chain, and update physical output buffers to drive external net lines.
A boundary scan register operating without full boundary access leaves unmapped pin transitions unmonitored during pattern execution.
Overall test coverage depends on how thoroughly compliant devices populate the netlist. Whenever non-compliant parts tie into boundary nets, structural visibility drops. Connectors, passive filter networks, discrete memory chips, and analog ICs carry no boundary registers, leaving connected signal paths partially or wholly unobservable during scan shifts.
- AC coupling capacitor blockage blocks direct current test voltages from propagating across high-speed differential pairs.
- Series damping resistor isolation attenuates logic swings below boundary scan receiver thresholds during pattern drive.
- Bus transceiver high-impedance states isolate downstream net segments from boundary scan driver cells during testing.
- Pull-up resistor termination leakage masks open-circuit faults by pulling floating traces up to high logic levels.
- Non-compliant component pin overhang introduces unobservable electrical nodes across mixed-technology boards.
Handling Complex Interconnect Topologies and Differential Signal Lines
Capacitively coupled traces and termination networks disrupt direct current boundary testing because they cannot pass sustained DC levels. High-speed gigabit serial lines rely on inline alternating current coupling capacitors to isolate DC bias voltages between transmitters and receivers. Standard boundary vectors apply steady direct current logic levels that charge these coupling capacitors and decay to indeterminate voltages at input receiver cells.
Testing capacitively coupled differential lines requires high-speed boundary extension architectures designed for AC signaling. Pulse-based stimulus algorithms drive rapid edge transitions across differential pairs, allowing hysteresis receivers to observe rising and falling pulse edges before capacitor charge accumulation dampens signal amplitude. Evaluating high-speed signal integrity demands pulse execution patterns that verify capacitance continuity without relying on static DC drive states.
While boundary scan coverage above eighty percent on the master bill of materials is often argued to eliminate physical probing, unmonitored traces and non-compliant pins still require mechanical access to guarantee fault detection.
Faults
Quantifying defect risk starts with extracting the electrical netlist from the layout data. Structural fault coverage balances detectable manufacturing defects against the total potential fault universe across all board nodes; omitting non-boundary pins from that denominator inflates coverage numbers and conceals escape risks.
Defining the Netlist Fault Universe Denominator
Layout extraction maps every component pin to its copper trace. The interconnect fault universe is measured from two distinct angles: pin-level stuck-at opportunities and net-level bridging opportunities. A board with a given number of component pins presents twice that figure in stuck-at opportunities, reflecting stuck-at-0 and stuck-at-1 states on every pin.
At the net level, the fault universe accounts for open connections and inter-net shorts. Theoretical bridging opportunities grow quadratically ~ calculated as total nets multiplied by total nets minus one, divided by two. Measuring coverage against this theoretical total artificially inflates the metric, since physical routing keeps traces on separate layers or distant regions from ever bridging.
Robust extraction tools restrict bridging models to adjacent trace segments identified from CAD layout geometry.
Net classification groups assembly traces across defined access profiles:
- CAD netlist parsing identifies every physical connection between component pads across all circuit board signal layers.
- BSDL file validation checks boundary scan description syntax against physical integrated circuit pinout mappings.
- Power net exclusion filtering removes ground planes and voltage supply rails from the active interconnect fault universe.
- Passive component mapping tags inline series resistors and inductors that connect adjacent net segments.
Mathematical Formulations for Net Level Coverage
Calculating boundary coverage involves dividing detected node faults by total potential structural defects. Net-level metrics weight nets according to their controllability and observability: fully covered nets with boundary cells at every terminal receive full credit, nets with at least two boundary pins get partial credit, and nets with fewer than two boundary pins receive zero credit.
Pin-level stuck-at fault coverage follows a strict binary formulation:
Pin Coverage Percentage = ( Detected Pin Stuck Faults / Total Assembly Pins Multipled By Two ) 100
Net-level interconnect fault coverage utilizes weighted node accounting across the board netlist:
Net Coverage Percentage = ( Two Times Fully Covered Nets + Partially Covered Nets ) / ( Two Times Total Extracted Nets ) 100
Higher boundary scan cell density directly reduces secondary in-circuit mechanical probing requirements.
Consider an industrial control board containing 1,500 total electrical nets and 6,000 component pins, where boundary scan integrated circuits control 4,200 package pins across the assembly. Net analysis identifies 900 fully covered nets where every attached component pin connects to a boundary scan cell. An additional 400 nets connect boundary scan pins to non-boundary scan memory devices, connectors, or passive networks, creating partially covered nets.
The remaining 200 nets comprise power rails, analog traces, and unmapped test points containing zero boundary scan access points.
Net-level coverage calculation for this assembly proceeds as follows:
Total Net Boundary Opportunities = 2 1,500 = 3,000 credit points.
Fully Covered Net Credit = 2 900 = 1,800 credit points.
Partially Covered Net Credit = 1 400 = 400 credit points.
Total Earned Net Points = 1,800 + 400 = 2,200 credit points.
Net Interconnect Fault Coverage = ( 2,200 / 3,000 ) 100 = 73.33 percent.
Pin-level stuck-at coverage calculation yields a different metric across the same board:
Total Pin Stuck Fault Opportunities = 2 6,000 = 12,000 potential stuck faults.
Detectable Boundary Pin Stuck Faults = 2 4,200 = 8,400 detectable faults.
Pin Stuck At Fault Coverage = ( 8,400 / 12,000 ) 100 = 70.00 percent.
| Net Category | Net Count | Pin Count per Net | Boundary Access Status | Net Level Coverage Credit | Effective Fault Coverage |
|---|---|---|---|---|---|
| Fully Covered Nets | 900 | All Pins Accessible | Full Control and Observe | 2 Points per Net | 100.0% |
| Partially Covered Nets | 400 | At Least 2 Pins Accessible | Partial Control or Observe | 1 Point per Net | 50.0% |
| Uncovered Digital Nets | 120 | 1 or 0 Pins Accessible | No Control or Observe | 0 Points per Net | 0.0% |
| Power and Analog Nets | 80 | 0 Pins Accessible | Bypassed by Scan Chain | 0 Points per Net | 0.0% |
| Total Assembly Interconnect Coverage: 73.33% across 1,500 extracted layout nets. | |||||
Comparing net-level coverage with pin-level coverage demonstrates why test documentation must state denominator definitions explicitly. Reporting a single percentage without specifying access constraints creates false confidence regarding true structural quality.
Evaluating partial net coverage on multi-drop buses with parallel pull-up networks remains contentious, as automatic pattern tools often struggle to resolve intermediate voltage levels predictably.
Arithmetic
Numerical metrics calculated during pattern simulation translate directly into manufacturing escape probability calculations. By coupling structural fault coverage with historical printed circuit board assembly defect density, engineers estimate how many solder defects will slip through to functional test or reach customer environments.
Escape Rate Derivation and Yield Projections
Defect probability models combine net coverage percentages with historical printed circuit board assembly defect density. Manufacturing defect density measures expected solder joint disconnections, bridges, and missing components expressed in defects per million opportunities. Calculating defect escape rates requires multiplying assembly defect density by the uncovered interconnect fault fraction.
On an SMT manufacturing line demonstrating a historical defect density of 450 defects per million opportunities across interconnect solder joints, the example assembly exhibiting 73.33 percent net interconnect fault coverage leaves an uncovered interconnect fraction of 1 minus 0.7333, or 0.2667.
Defect Escape PPM = 450 ( 1 – 0.7333 ) = 120.015 defects per million assemblies shipped.
An escape rate of 120 PPM forces downstream functional test stations to catch structural disconnections. Because functional test stations exhibit poor diagnostic resolution and fixture wiring introduces stray capacitance, isolating simple solder bridges consumes extended bench hours. Calculating escape risk identifies where supplementary test regimes are required to protect assembly yield.
Multi-Regime Overlap and Complementary Defect Detection
In-circuit testing and flying probe inspection capture disconnections on nets outside boundary scan access chains. Combining boundary scan testing with secondary physical probing eliminates coverage gaps across partially covered and uncovered nets. When flying probe inspection targets nets lacking boundary cells, total assembly defect escape rates drop dramatically.
Compliance with IPC 9252 class three electrical test requirements obligates manufacturers to verify non-accessed nets through secondary physical probing.
Assume a flying probe routine targets the 600 partially covered and uncovered nets identified in the netlist analysis, achieving 80 percent coverage across those specific unmapped nodes. The residual uncovered net fraction drops according to combined regime probability equations:
Combined Uncovered Fraction = ( 1 – 0.7333 ) ( 1 – 0.8000 ) = 0.2667 0.2000 = 0.05334.
Combined Defect Escape PPM = 450 0.05334 = 24.003 defects per million assemblies shipped.
- Extract the complete bill of materials and board design netlist from manufacturing file packages.
- Match all boundary scan component part numbers with verified vendor description files.
- Execute boundary scan test pattern generation software to produce interconnect vector suites.
- Calculate net level and pin level fault coverage percentages using extracted netlist statistics.
- Identify all unobservable and uncontrollable nets requiring secondary physical bed of nails or flying probe coverage.
Layering complementary test methods cuts field defect exposure by an order of magnitude, optimizing fixture development costs against field return reserves.
Test plans that rely solely on boundary scan without secondary probing inevitably pass assemblies containing open circuits on unmapped connector pins into final customer enclosures.
Filing
Authorizing production shipments requires verifiable boundary scan report artifacts attached directly to batch serial records. Quality management standards demand documented proof of electrical structural verification prior to commercial lot release. Unquantified coverage metrics invalidate certificate of conformance declarations and expose buyers to unrecoverable warranty claims.
Technical Dossier Elements for Interconnect Verification
Conformity records require detailed ATPG execution output log analysis alongside verified Boundary Scan Description Language documents. BSDL files define pin assignments, register lengths, and supported IEEE instructions for every boundary scan component on the assembly. Verification engineers validate BSDL syntax against silicon revision codes before compiling vector patterns.
A hash mismatch between layout netlists and BSDL declarations invalidates ATPG execution output.
A compliant interconnect test dossier contains specific verifiable records:
1. Boundary Scan Description Language validation reports with source file checksums and silicon package pin matching logs.
2. Complete CAD netlist extraction files detailing total nets, total pins, and component boundary access tags.
3. ATPG compilation execution logs listing applied pattern algorithms, generated vector volume, and targeted fault types.
4. Net-level and pin-level fault coverage reports breaking down fully covered, partially covered, and uncovered nets.
5. Serialized execution logs capturing test access port controller register values, shift frequency, and pass/fail status per board assembly.
Commercial Impact of Unquantified Interconnect Risk
Warranty reserves expand rapidly when untested printed circuit board traces experience latent field failures. Escaped interconnect defects that bypass factory testing trigger expensive field service calls, commercial line stoppages, and product recall liabilities. Quantifying netlist interconnect fault coverage establishes legal proof that appropriate structural defect screening occurred prior to market distribution.
Contract manufacturing agreements specify fault coverage thresholds necessary to fulfill yield guarantees. When boundary scan reports document unhandled coverage gaps, assembly vendors must supply complementary flying probe or optical inspection records to clear shipment holds. Attaching complete ATPG diagnostic dossiers to batch records ensures transparent quality auditing and protects commercial buyers against latent defect liabilities.
Under standard international manufacturing procurement agreements, section twelve line four specifies that unverified interconnect coverage voids supplier warranty obligations for field-returned assemblies.