Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
Net Level Fault Universe
Defect Framing
Exhaustive structural defect modeling that defines every hypothetically possible short circuit and open circuit condition across a printed circuit board assembly frames test program completeness. In automated electrical testing, a net level fault universe establishes the mathematical set of physical defects that an unpopulated or assembled board could present. Test generation algorithms parse CAD netlists to identify all conductive node pairs capable of experiencing bridge defects or continuity breaks.
Quality engineers use this mathematical set to evaluate the theoretical maximum fault coverage of bed-of-nails and flying probe test fixtures.
Coverage Mapping
Calculating complete fault sets requires analyzing trace geometry, adjacent net proximity and component pin counts across the entire circuit layout. Within a net level fault universe, open circuit faults represent broken electrical continuity along single conductive paths, while short circuit faults represent unintended low resistance bridges between distinct nets. Adjacency rules filter out physically impossible short circuits between traces separated by wide dielectric clearances, reducing computation time during test pattern generation.
Flying probe testers utilize these net models to optimize probe movement paths, prioritizing high probability fault sites during structural screening. Incomplete netlist extraction leads to unmodeled fault locations, yielding false positive coverage reports during production acceptance testing. Structural testing coverage software calculates the exact percentage of modeled faults detected by specific boundary scan and in-circuit test routines.
Boundary Metrics
Uncovered fault nodes identify circuit areas requiring secondary inspection methods like automated optical or X-ray inspection. Modifying component layout spacing eliminates high risk short circuit locations identified during netlist fault extraction. Final test acceptance criteria require complete detection reporting across all defined netlist fault categories.