Quantifying Netlist Interconnect Fault Coverage Using Boundary Scan ATPG Vectors
Quantifying boundary scan interconnect fault coverage pairs extracted netlist node universes with modified counting sequence vector execution logs.
ATPG Vectors
Digital Stimulus
Binary patterns generated by automated software tools provide the inputs required to test integrated circuits for manufacturing defects. These automated test pattern generation vectors, commonly known as ATPG vectors, are applied to the scan chains of a completed board during boundary scan test operations. Their purpose is to excite potential physical faults and propagate the results to observable output pins.
Fault Model
Mathematical representations of physical manufacturing failures define the targets of the generation process. When generating ATPG vectors, algorithms target specific faults such as stuck-at or transition delay anomalies. By focusing on these defined electrical misbehaviors, the test generation engine systematically builds patterns that isolate faults.
This targeted approach prevents the escape of defective silicon into final assembly.
Pattern Execution
Production testers deliver the precomputed signals to the device under test through a physical interface. This execution relies on precise timing and synchronized tester channels to apply the ATPG vectors to the silicon. If a scan chain is broken, the vector fails to load correctly, indicating a localized physical defect.
High pin-count devices require massive pattern sets to achieve acceptable test coverage. Testers then evaluate the output sequences against expected vectors stored in memory to identify failed assemblies before shipment.