Interface Protocol
Serial test interfaces compliant with standard IEEE 1149.1 definitions provide access to internal boundary scan registers within complex integrated circuits. Board-level structural testing requires dedicated physical connections to exercise component pins without physical probe contact. The boundary scan tap operates through a five-wire serial bus comprising test clock, test mode select, test data input, test data output and optional reset lines.
This functional interface stops at the chip boundary and boundary scan register architecture, leaving analog circuits and non-compliant silicon unaddressed.
State Controller
Internal state logic advances through sixteen distinct states driven by transitions on the test mode select input during test clock edges. Control sequences shift instruction codes into the instruction register or transfer data through boundary scan cells surrounding internal device logic. Using the boundary scan tap allows structural interconnect testing across assembled circuit boards by driving test patterns out of one IC pin and capturing them at an adjacent receiving pin.
Test software reads captured register states to identify open solder joints, pin shorts and damaged input drivers on assembled circuit boards. Clock speeds during shift operations are governed by trace length and capacitance along the dedicated scan bus on the board layout. Dedicated ground planes adjacent to test clock traces prevent false state machine transitions caused by crosstalk during vector execution.
Register Access
Instruction codes loaded through the test interface enable specific operational modes including bypass, sample, preload and boundary test. The bypass register reduces the scan chain length to a single bit when specific devices require no testing during a test pass. Test engineers use instruction register updates to isolate components during in-circuit testing.
