False Call Rates That Decide Whether AOI Earns Its Place
AOI earns its place on an SMT line only when false calls stay below 200 PPM, preventing operator fatigue and protecting manual retouch benches from destroying good joints.
Component Coplanarity
Assembly Tolerance
Measured vertical deviation from a perfect plane defines the positional alignment of pins on a multi-lead integrated circuit package during surface mount placement. Component coplanarity governs the threshold at which these leads fail to make physical contact with printed solder paste deposits. Surface mount technology relies on this metric to avoid open circuits or cold joints that prevent proper electrical conduction.
Manufacturing specifications define a ceiling for vertical offset, typically expressed in micrometres or mils. Exceeding this boundary during the reflow process stops the formation of a fillet. Automated optical inspection stations detect these deviations by calculating the height difference between the lowest lead and all other terminals on the package body.
Placement Dynamics
High density arrays require strict control over lead geometry to ensure that every terminal settles into the dispensed paste volume. A warped lead frame shifts the entire package off the target datum, which prevents the meniscus formation required for a solder joint. Precision pick and place equipment cannot compensate for physical deformation of the leads if the offset falls outside the programmed capture window.
Solder paste volume displacement often occurs when an angled lead pushes through the deposit without wetting the pad surface. Engineers verify this physical state by using laser scanning or shadow projection methods before the boards enter the thermal chamber. Tightening the tolerances here ensures that every connection point arrives at the board surface with uniform pressure.
Variations in thermal expansion rates between the ceramic or plastic housing and the metal leads increase the risk of lifting during the cooling phase of the cycle.
Inspection Integrity
Failure to maintain the plane results in non-wetting conditions that force rework or rejection of the entire assembly. Quality control protocols evaluate each batch by measuring the distance from a reference plane to the bottom of the seated leads. These inspections verify the integrity of the seating plane while the component rests on a flat simulation surface.
Proper management of lead height distribution guarantees that the mounting process achieves the electrical connectivity demanded by the circuit design. Constant monitoring of lead flatness prevents manufacturing waste and ensures that final hardware performance remains stable across the entire production run.