Substrate Imperfection
Unfilled cavities located within laminated insulating layers reduce electrical breakdown strength and alter local dielectric constants. Multilayer printed circuit board fabrication processes monitor dielectric voids to maintain controlled impedance and electrical insulation across adjacent copper planes. This structural boundary excludes outer surface soldermask pinholes or surface conformal coating bubbles.
Breakdown Risk
Resin flow during lamination must fill spaces surrounding inner layer copper traces without trapping air or volatile organic gases. When prepreg resin fails to flow completely into gaps between dense copper features, dielectric voids remain permanently trapped inside the cured glass laminate structure. Cross-sectional micro-section analysis and high frequency time-domain reflectometry reveal localized drops in dielectric strength where voids distort electric fields.
High voltage stress testing induces partial discharge inside these gas cavities, eroding surrounding epoxy resin and causing dielectric breakdown between power layers. Moisture absorption inside void cavities during solder reflow generates internal steam pressure, leading to substrate delamination and blister formation.
Fabrication Limit
Impedance calculations for high speed microstrip and stripline traces assume uniform dielectric permittivity throughout insulating laminates. Voids distort signal propagation velocity and lower characteristic trace impedance. Rigid incoming substrate inspection standards limit void size and frequency across high layer count boards.
