Degradation Mechanism
Progressive material displacement along conducting metal pathways arises from sustained momentum transfer between flowing conduction electrons and diffusing metal lattice atoms under high current densities. In surface mount assemblies, electromigration fatigue describes the progressive structural breakdown of interconnects, solder bumps and fine-pitch printed traces subjected to simultaneous electrical drift and thermal stress. Direct electron momentum forces metal atoms toward the anode, generating corresponding vacancies that drift toward the cathode.
Vacancy coalescence initiates sub-micron voids along high-flux regions, reducing the effective conductor cross-section and escalating local current concentration. The damage cycle accelerates exponentially because increased localized resistance creates Joule heating that drives further vacancy migration.
Failure Progression
Metal atom transport alters the structural integrity of solder joints across hundreds of operational hours. Microscopic voids nucleate primarily along intermetallic compound boundaries, expanding into continuous planar cracks adjacent to the component metallization layer or printed circuit land pad. At the opposing terminal, mass accumulation builds compressive stress that extrudes metallic hillocks and whiskers across dielectric gaps, establishing intermittent or permanent electrical shorts.
Accelerated life testing applies elevated ambient temperatures alongside high current densities to project mean time between failures through Black’s equation. Visual inspection using scanning electron microscopy reveals asymmetric consumption of copper or nickel barrier layers across opposing polarity joints within the same package.
Design Rule
Current density limits specified in high-reliability assembly designs restrict trace and via loading to prevent atom migration thresholds from being exceeded. Specifying nickel immersion gold or nickel-palladium-gold finishes supplies a stable diffusion barrier that decelerates metal consumption. Board layouts for power stages mandate parallel conductor routing and redundant via arrays to distribute current flux uniformly across the entire interconnect boundary.
