Electromagnetic Field Suppression in Multilayer Printed Circuit Power Plane Stackups
Thin dielectric power plane pairs suppress high frequency cavity modes and radiated emissions by lowering target impedance and shifting resonant frequencies.
Embedded Capacitance Laminate
Substrate Material
Substrate material consisting of ultra-thin dielectric layers sandwiched between copper foils provides distributed capacitance across the entire plane of a printed circuit board. Using embedded capacitance laminate allows designers to remove discrete decoupling capacitors from the board surface to free up area for active components. This material consists of a high-permittivity resin pressed between layers of copper to form a functional power-ground sandwich.
Electrical Performance
High frequency noise suppression improves because the internal plates provide a low-impedance path for current surges. Because the embedded capacitance laminate is integral to the stackup, it eliminates the lead inductance associated with surface-mount device pads and vias. This configuration reduces electromagnetic interference and stabilizes voltage rails during rapid switching events.
Signal integrity remains consistent across the plane.
Fabrication Constraint
Processing these thin cores requires specialized handling equipment to prevent wrinkles or damage during the inner layer etching and lamination cycles. Standard thickness for the dielectric layer often ranges from 8 to 25 microns. Thinner layers increase the total capacitance per square inch but also raise the risk of electrical shorts if particles contaminate the resin.
High-voltage insulation testing must be performed on every panel to ensure the integrity of the dielectric barrier before final assembly. Yield losses occur if the registration of the power and ground layers shift even slightly during the pressing stage.