Boundary Scan Integration for High Density Circuit Assemblies
Boundary scan integration replaces physical test points with silicon registers, securing structural fault coverage on high density circuit assemblies.
EXTEST Mode
Boundary State
Boundary scan test architectures provide hardware access to device pin states during board-level interconnect verification. Selecting extest mode isolates internal core logic from external package pins, driving boundary cells directly from the instruction register. The operational state enables structural testing of circuit board traces without applying functional power to on-chip processing cores.
Interconnect Scan
Test patterns load into boundary register cells through the test data input pin while the TAP controller sequences through update states. Output drivers force logic high or low levels onto circuit board nets, while adjacent receiving pins capture physical voltage states into input cells. Structural defects such as open solder joints, solder bridges, and unbonded trace networks reveal themselves through mismatched test data output streams.
Extended net networks spanning multiple integrated circuits test sequentially without requiring physical bed-of-nails probe contact. Boundary scan clock frequencies dictate test execution speed, balancing signal integrity against driver switching noise. Board designs incorporating non-scannable clusters rely on scannable driver pins to inject test vectors into surrounding logic gates.
Pin Control
High impedance pin states prevent output bus driver contention during test vector shifting across shared data lines. Driving conflicting logic levels onto a single net damages driver transistors through excessive current draw. System clocks remain disabled during test execution to prevent internal state changes while boundary cells control package pins.