Modeling Dynamic Parasitic Loading Effects on Scan Network Timing Margins
Dynamic parasitic extraction during ATPG shift prevents false timing violations by accounting for state-dependent capacitance and power rail collapses.
Glance Toggle Activity
Power Approximation
Estimates of average switching rates provide a metric for assessing power consumption without requiring exhaustive logic simulation. Using glance toggle activity allows designers to identify high power regions of a chip early in the development cycle. This approach uses statistical weights based on the logic depth and connectivity instead of specific input vectors.
Activity Calculation
Data for these estimates is derived from the netlist and the expected clock frequency of each domain. During the calculation of glance toggle activity, the tool assigns probabilities to each node based on the likelihood of a logic transition occurring within a given timeframe. This provides a fast way to evaluate the impact of different architectural choices on the thermal profile of the device.
Engineers often use these results to guide the placement of blocks to avoid creating hot spots on the die. The software uses these probabilities to estimate the toggle rate for thousands of nodes in seconds.
Analysis Constraint
Speed of execution makes this method suitable for large designs where full vector simulation is too time consuming. While glance toggle activity provides a useful overview, it lacks the precision needed for fine-grained timing or peak current analysis. The results are used as a filter to determine which areas of the circuit require more detailed investigation using vector-based tools.