False Call Rates That Decide Whether AOI Earns Its Place
AOI earns its place on an SMT line only when false calls stay below 200 PPM, preventing operator fatigue and protecting manual retouch benches from destroying good joints.
Height Reference Plane
Plane Boundary
Spatial geometry dictates z-axis clearance during surface mount device placement on populated printed circuit boards. The height reference plane establishes the zero elevation datum from which component body clearances are measured by optical inspection systems prior to reflow soldering. Optical coordinate measurement routines project this baseline across fiducial markers located on the bare board laminate to compensate for inherent substrate bow and twist.
Vertical displacement values exceeding programmed tolerances above this datum trigger automated optical inspection flags for co-planarity failures or lifted leads. Manufacturers establish this parameter within machine recipes before initializing high speed placement equipment to protect fragile ceramic capacitors from mechanical overload caused by excessive nozzle travel.
Clearance Control
Component body thickness variations demand precise calibration relative to the established datum to prevent physical collisions between placement heads and adjacent tall connectors. Z-axis travel limits enforce strict boundaries that halt machine cycles whenever a component profile exceeds the allowable vertical envelope above the reference surface. Substrate warpage introduced during infrared reflow heating alters the local elevation of pads, which forces vision systems to recalculate the baseline dynamically across different panel zones.
Laser displacement sensors scan the bare circuit board topography immediately preceding component deposition to map localized deviations and adjust placement head descent profiles accordingly.
Inspection Verification
Automated optical inspection equipment relies on projected fringe patterns to evaluate solder fillet formation and component standoff heights relative to the underlying board geometry. Height verification algorithms compare captured profile data against theoretical thresholds derived from computer aided design models linked to the established baseline. Laser profilometry scans completed assemblies post-reflow to quantify solder volume distribution and detect bridging defects hidden beneath low clearance integrated circuit packages.
Quality control engineers analyze these topographical maps to identify warped laminate lots before subsequent functional test stages reject electrically defective assemblies.