Standardizing Glass Fabric Specifications for High Speed Printed Boards
Standardizing spread Low-Dk glass fabrics eliminates phase skew and stabilizes trace impedance across high-speed printed circuit board panels.
High-Speed Panel Yield
Production Metric
Manufacturing efficiency is calculated by the ratio of functional circuit boards to the total number of units started on a production sheet. Maintaining high-speed panel yield requires strict control over dielectric thickness and trace width tolerances to meet impedance specifications. In high-performance applications, even a small deviation in material properties can render a board unusable for its intended data rate.
This metric directly influences the final cost of the assembly by determining the amount of waste generated.
Loss Mechanism
Rejection of panels often occurs during the electrical test phase when traces fail to meet the required ohmic or signal integrity benchmarks. Variations in the plating process can cause uneven copper thickness, leading to impedance mismatches across the surface of the panel. Misalignment of the internal layers also contributes to failure by creating parasitic capacitance or inductance that was not accounted for in the original simulation.
These defects are more common in boards with high layer counts and dense routing. Continuous monitoring of the etch compensation helps to mitigate these risks.
Cost Optimization
Improving the success rate involves selecting materials with low loss tangents and stable thermal properties. Manufacturers often run test coupons on the edge of the panel to verify the process window.