Quantifying Microstrip Phase Delay Variance Driven by Prepreg Glass Yarn Geometry
Prepreg glass bundle spacing causes local permittivity shifts that introduce picosecond phase delay variance in high-speed microstrip traces.
High Speed Stackup
Multilayer Arrangement
Layer arrangements in multilayer printed circuit boards are structured to support rapid signal transitions without degradation. A high speed stackup optimizes the sequence of copper layers, prepreg, and core materials to provide controlled impedance paths. This arrangement positions signal traces adjacent to continuous reference planes.
Signal Integrity
Signal transmission at gigahertz frequencies requires precise control over the physical dimensions of the dielectric layers and copper foils. In a high speed stackup, dielectric materials with a low dissipation factor are selected to prevent signal attenuation over long traces. Thin laminate cores are utilized next to power and ground planes to increase interplanar capacitance, which helps decouple the power distribution network.
The spacing between layers is engineered to keep trace widths within practical manufacturing limits while meeting target impedance requirements.
Manufacturing Constraint
Thermal and mechanical stability must also be addressed during the fabrication of these complex multi-layer boards. When fabricating a high speed stackup, sequential lamination cycles and asymmetric layer distributions can introduce warpage or registration errors during drilling. Fabricators mitigate these risks by using materials with matched coefficients of thermal expansion and balancing the copper weight across the board center-line.
Regular testing with time-domain reflectometry ensures that the produced board conforms to the design specifications. High-frequency performance relies on these structural details.