Scan Architecture
Embedded test access technology based on variable boundary scan chains enables efficient communication with monitoring instruments integrated inside silicon chips. The system known as IJTAG provides the structural description and control flow necessary to manage these internal instruments without relying on traditional boundary scan limitations. By introducing dynamic segments into the test register paths, this architecture simplifies the testing of complex system on chip boards.
Instrument Access
Command generation for embedded sensors utilizes specialized languages to automate test sequences across various hardware platforms. When a board is tested, IJTAG instruments such as temperature sensors and phase locked loop monitors receive commands via procedural description language. The control system routes these packets through dynamic scan paths described by instrument connectivity language.
This allows test engineers to run self tests on specific silicon subblocks during board level debugging without requiring manual test generation or direct physical access to the high speed signals.
Diagnostic Value
Diagnostic resolution during board assembly verification increases when on chip instruments can detect failures that external probes cannot reach. Board level test development relies on these internal instruments to verify high speed transceivers and internal memory interfaces directly from the boundary scan controller. This reduces the need for expensive external test points on high density circuit boards.
