Performance Envelope
Standardized limits for trace impedance variations dictate the acceptability of printed circuit boards processed on a production line. The specific deviation allowed from the nominal target is termed the impedance coupon tolerance, which is evaluated on test strips located on the panel borders. This boundary is typically specified as a percentage of the design impedance, with ten percent being standard and five percent used for high-reliability military or aerospace projects.
If the measured impedance of a coupon falls outside these limits, the entire panel is subject to rejection. This ensures that the high-frequency performance of the actual board traces, which cannot always be probed directly, remains within the simulated parameters.
Fabrication Variable
Substrate thickness variations and copper etching profiles are the primary drivers of coupon measurements. Even minor changes in the width of a trace during the acid etching stage will alter the capacitance and shift the final coupon impedance. Resin flow during lamination also modifies the dielectric layer height.
Panel designers position coupons carefully to ensure they undergo identical processing conditions to the functional board traces.
Verification Method
Time-domain reflectometry uses a fast-rise-time step generator to measure reflections along the test coupon trace. This non-destructive test exposes any localized impedance variations along the conductor path. The trace must run at least five inches to allow the reflectometer pulse to settle for a stable reading.
High-precision probes and calibrated launch points minimize measurement noise during this quality inspection.