Layer Alignment
Photolithographic alignment defines the lateral positional accuracy between conductive copper features and the drill holes or vias on separate inner layers of a printed circuit board. Internal core registration controls the physical shift occurring when the thin core substrate undergoes thermal expansion during the lamination process. Deviations in this positional accuracy result in open circuits or reduced annular rings that compromise the reliability of the finished interconnect.
Precise mechanical pins and optical alignment systems minimize the offset between these features before the stackup enters the press.
Tolerance Specification
Mechanical constraints dictate the maximum allowable displacement for internal features relative to the primary datum points established on the board edge. Fabricators calculate this internal core registration by measuring the distance between the center of a via hole and the center of the matching capture pad located on the inner layer after etching. Excessive movement beyond the design rule values triggers a rejection of the entire panel as the signal path lacks the necessary contact area.
Standard production requirements often restrict this variance to a percentage of the dielectric thickness to preserve signal integrity.
Process Verification
Automated optical inspection equipment detects these deviations by scanning the copper patterns on each core layer prior to the bonding phase. Inspectors verify the alignment by overlaying the captured image with the original drill file data to quantify the registration error. Technicians adjust the tool compensation factors or modify the tooling hole sizes to counteract the predictable shifting of the material under heat and pressure.
Proper control of this variable prevents manufacturing defects that emerge after the assembly process when electrical continuity becomes impossible to restore.