Modeling Dynamic Parasitic Loading Effects on Scan Network Timing Margins
Dynamic parasitic extraction during ATPG shift prevents false timing violations by accounting for state-dependent capacitance and power rail collapses.
Launch off Capture
Test Sequence
Delay test methodologies utilize two successive clock pulses within the functional domain to detect transition faults at operational speeds. The launch off capture technique is used in many scan designs because it provides an assessment of the path delays during normal circuit operation. This method relies on the functional logic of the chip to generate the transition rather than the scan shift clock.
Sequence Execution
Implementation begins by shifting a known test pattern into the scan chain at a low frequency. Once the chain is loaded, the launch off capture process uses a first clock pulse to launch a signal transition and a second, high speed pulse to capture the result in the next flip-flop. The timing between these two pulses matches the target operational frequency of the device.
Special care is taken to ensure that the clock distribution network can deliver these pulses with minimal skew across the entire chip. Automated pattern generators calculate the required logic states to sensitize the path between the two flip-flops.
Fault Coverage
Efficiency of this method is measured by its ability to detect slow-to-rise or slow-to-fall defects that might bypass standard static tests. Using launch off capture ensures that the device can operate at its rated speed under real-world conditions. While the generation of patterns for this technique is complex, the quality of the resulting test is required for high reliability applications.