Layer Verification
Cross-sectional metallography reveals internal anomalies that exterior visual checks miss entirely. Microsection alignment inspection targets printed circuit board multilayer registration by measuring dielectric spacing and drill breakout on polished coupons. Internal layer shifting compromises plated through hole reliability during thermal shock exposure.
Plating thickness and copper foil anomalies emerge under magnification alongside registration offsets. Destructive sample preparation remains necessary because optical tools cannot penetrate opaque laminate stacks.
Registration Tolerance
Manufacturing variability produces acceptable offsets within defined engineering limits. Microsection alignment inspection quantifies layer displacement against fabrication drawings and IPC specifications. Annular ring breakout calculations derive from measured copper web dimensions visible in the prepared epoxy mount.
Etching asymmetry and lamination shift combine to alter positional accuracy across the panel surface. Acceptance criteria establish maximum allowable displacement percentages before barrel cracking occurs under thermal stress.
Coupon Fabrication
Production panels incorporate sacrificial coupons along outer panel margins specifically for destructive evaluation. Microsection alignment inspection relies on these witness strips experiencing identical thermal and mechanical processing as functional circuits. Resin encapsulation supports copper features during grinding and polishing steps to prevent edge rounding artifacts.
Chemical etching highlights grain boundaries and dielectric interfaces for measurement under calibrated optical microscopes. Destructive physical analysis guarantees compliance when electrical testing yields ambiguous results regarding internal continuity.
