Alignment Error
Alignment errors between the two signals of a differential pair result in timing offsets that degrade the quality of the communication link. Microstrip phase skew is particularly sensitive to the local environment because the conductors are on the outer layers where they are exposed to variations in solder mask thickness and air.
Intersymbol Interference
Intersymbol interference and increased jitter are the results of this timing mismatch at the receiver. When microstrip phase skew exceeds a small fraction of the bit period, the eye diagram closes and data recovery becomes impossible.
Material Influence
Material influence is the most common cause of this problem, specifically the glass-weave effect within the laminate. High-speed designers specify spread-glass fabrics or use a zig-zag routing style to ensure that each trace in the pair sees the same ratio of glass and resin. Measuring the skew with a high-bandwidth oscilloscope or a time-domain reflectometer confirms that the manufacturing process has stayed within the timing budget.
If the skew is too large, the board is often scrapped because there is no way to fix the timing once the traces are etched. This verification is a requirement for all boards supporting PCIE or Ethernet protocols.