Modeling Dynamic Parasitic Loading Effects on Scan Network Timing Margins
Dynamic parasitic extraction during ATPG shift prevents false timing violations by accounting for state-dependent capacitance and power rail collapses.
Miller Capacitance Scaling
Capacitive Multiplier
Increases in the effective input capacitance of an inverting amplifier result from the feedback path between the input and output nodes. The phenomenon of miller capacitance scaling occurs because the voltage across the feedback capacitor changes by a factor equal to one plus the gain of the amplifier. This effect reduces the bandwidth of high gain stages and must be accounted for in both analog and digital circuit designs.
Scaling Physics
Calculation of the total input capacitance involves adding the base capacitance to the product of the feedback capacitance and the voltage gain. During the design of an integrated circuit, miller capacitance scaling is used to predict the transition times of logic gates and the frequency response of amplifiers. Large gains lead to a large increase in the perceived capacitance, which in turn slows down the input signal.
Designers often use cascode configurations or other circuit topologies to minimize this effect. High speed buffers are placed before the gain stage to drive the increased capacitive load.
Circuit Impact
Management of these parasitic properties is necessary to achieve high speed operation in modern semiconductor devices. If miller capacitance scaling is ignored, the resulting circuit will likely suffer from excessive signal delay and reduced stability. Verification tools extract these values from the layout to ensure that the final performance matches the design objectives.