Capacitive Model
An electrostatic structure formed by two flat conductive sheets separated by a uniform dielectric layer stores electrical charge and determines the impedance of a board power distribution network. The parallel plate capacitance of this structure is proportional to the area of the overlapping conductors and the permittivity of the insulating layer, and inversely proportional to the distance between them. In printed circuit boards, this configuration is created by pairing closely spaced power and ground planes to provide distributed high-frequency decoupling across the entire assembly.
It suppresses voltage fluctuations caused by rapidly switching digital components.
Decoupling Mechanism
Placing the power and ground planes extremely close together increases the capacitance of the plane pair while simultaneously reducing the loop inductance of the power delivery path. This physical proximity allows the plane capacitance to supply rapid transient currents to switching integrated circuits during the sub-nanosecond rise times where discrete decoupling capacitors are ineffective due to their lead inductance. To achieve high capacitance values, fabricators utilize very thin laminate materials, sometimes under twelve microns in thickness, with high relative permittivity.
However, these thin dielectrics require careful handling during fabrication to prevent microscopic defects or conductive debris from causing electrical shorts between the planes.
Board Diagnostics
Measuring this capacitance across the printed circuit board panel provides a non-destructive method for verifying the thickness uniformity of the dielectric core during fabrication. If the measured capacitance varies across the board, it indicates that the resin has been distributed unevenly during the lamination cure cycle. This diagnostic check allows operators to adjust the lamination parameters for future production runs to maintain consistent layer thickness.