Solder Mask Gloss Variances That Trigger False Optical Defects
Solder mask gloss shifts distort automated optical inspection light scattering, generating false defect calls that drop assembly line throughput.
PCB Incoming Quality Control
Material Verification
Material verification stands as the primary defensive barrier against defective substrate and metallization entering a printed circuit board assembly line. Raw laminates and bare boards arrive from external fabricators where optical inspection and electrical continuity testing must happen before any surface mount technology placement begins. This verification procedure checks incoming shipments against purchase order specifications, engineering drawings, and IPC standards.
Fabricators deliver bare boards with specific copper weights, solder mask parameters, and dielectric thicknesses, and incoming quality control confirms these physical traits match design intent. A laminate exhibiting excessive moisture absorption or incorrect glass transition temperature fails verification immediately because thermal stress during reflow soldering would delaminate the layers.
Defect Classification
Defect classification categorizes board anomalies into critical, major, and minor deviations based on functional impact during downstream manufacturing. A critical defect prevents electrical continuity or assembly, such as missing through-hole plating or inner layer shorts, and warrants total lot rejection. Major defects affect reliability without stopping production immediately, including annular ring breakout, solder mask encroachment on pads, or warp exceeding percentage thresholds.
Minor deviations involve cosmetic blemishes that do not violate IPC workmanship standards, allowing material disposition through engineering review. Operators document dimensional non-conformances using microscopic measurement equipment, comparing hole diameters and board edges against tolerance limits defined in fabrication drawings.
Acceptance Protocol
Acceptance protocol establishes the statistical sampling plans and lot disposition rules governing the release of bare boards to the factory floor. Quality engineers apply acceptable quality limit tables from standard sampling frameworks to determine sample sizes based on lot quantities. Random sampling ensures every box in a shipment receives equal probability of selection for destructive and non-destructive testing.
Lots meeting defect thresholds transfer to inventory storage with verified status, whereas failing lots receive segregation labels and return documentation for supplier corrective action. This systematic gate prevents non-conforming substrate from causing downstream assembly failures.