Pulse Modulation
Sixth generation serial bus technology introduces four level signaling to double the data rate without doubling the frequency. The pcie 6.0 standard uses pulse amplitude modulation to pack two bits of data into every clock cycle. This shift from binary signaling allows the interface to reach sixty four gigatransfers per second while operating within the same frequency envelope as previous versions.
Error Correction
Smaller voltage margins between the four states make the signal more susceptible to noise and interference. A forward error correction mechanism is built into the protocol to identify and fix bit errors in real time. This is a departure from earlier generations that relied primarily on the physical quality of the channel to prevent errors.
Because the error correction adds latency, the logic and the physical layer must be tightly integrated to maintain the performance of the bus.
Lane Throughput
Demands on the printed circuit board are extreme because any ripple in the frequency response can destroy the multi level signal. Low loss materials and precision fabrication are necessary to keep the signal noise floor as low as possible. The standard is intended for use in high performance data centers and artificial intelligence accelerators.
