Interconnect Design
Physical routing requirements for the sixth generation of the Peripheral Component Interconnect Express standard govern how 64 gigatransfers per second signals are managed on a board. A pcie gen 6 layout must support PAM4 signaling which is much more sensitive to noise and loss than the NRZ signaling used in earlier versions. This standard demands a rigorous approach to stackup and trace geometry.
Success Variable
Success in a pcie gen 6 layout requires the use of ultra-low-loss laminates and very smooth copper foils to keep the channel reach acceptable. Designers must eliminate all vias where possible or use advanced backdrilling to prevent reflections from stubs. The impedance must be held within a very tight window to minimize the return loss at the 16 GHz Nyquist frequency.
Surface roughness of the copper is a major contributor to signal attenuation at these speeds. Special care is taken at the transition from the silicon package to the board to ensure that the breakout region does not introduce excessive crosstalk.
Validation Metric
Validation of a pcie gen 6 layout involves measuring the signal eye diagram and the bit error rate. The complex modulation requires sophisticated equalization at both the transmitter and the receiver to maintain a stable link.