Substrate Defect Attributable Scrap Clawback Formulas in High Density Interconnect Quoting
HDI scrap clawback formulas isolate raw substrate flaws from process loss to recoup unrecovered value-add costs across sequential lamination steps.
Sequential Lamination Yield Loss
Fabrication Scrap
Multilayer rigid printed circuit board production generates sequential lamination yield loss when successive press cycles destroy previously bonded inner layers through registration drift or dielectric voiding. Mechanical alignment tolerances accumulate across repeated thermal presses, forcing manufacturers to discard panels that exceed copper feature displacement limits during optical inspection. High density interconnect fabrication introduces specialized press cycles to build sequential subassemblies, where each additional pressing operation multiplies the statistical probability of core delamination and resin starvation.
Thermal expansion mismatches between cured FR4 cores and unreinforced prepreg sheets generate residual stresses that fracture inner layer copper traces during cooling phases.
Registration Drift
Optical alignment systems measure sequential lamination yield loss by comparing fiducial mark locations on inner layers before and after high temperature press cycles. Glass transition temperatures of partially cured dielectric materials dictate the dwell time required inside vacuum hydraulic presses to prevent excessive resin flow from migrating away from circuit features. Photoplotters scale artwork compensation factors to counteract the dimensional shrinkage that occurs during each successive thermal excursion, yet unpredictable fiberglass weave directionality produces non linear distortion across large panel formats.
Automatic optical inspection machines flag positional errors exceeding specified thresholds, separating salvageable panels from scrap destined for mechanical recycling.
Thermal Defect
Destructive physical analysis confirms sequential lamination yield loss through microsectioning cross validation, revealing resin starvation pockets and inner layer barrel cracking caused by z axis expansion during subsequent wave soldering or infrared reflow exposure. Microvia reliability depends entirely on press pressure uniformity, because localized pressure gradients trap volatile outgassing byproducts inside blind via targets and cause subsequent plating blowouts. Controlled impedance calculations incorporate dielectric thickness variations measured across successfully laminated panels to adjust outer layer etching parameters before final solder mask application.
Electrical testing networks isolate surviving circuits from panels compromised by sub surface blisters, preventing defective multilayer boards from reaching final assembly lines.