Extracting Out-Of-Plane Dielectric Tensor in Heterogeneous Packaging Core
Extracting out-of-plane permittivity requires guarded parallel-plate or re-entrant cavity tests to isolate vertical flux fields from in-plane glass weave effects.
Spatial Anisotropy
Directional Variation
The directional dependence of material properties within a substrate results in non-uniform behavior along different physical axes of the printed circuit board assembly. In woven glass-reinforced laminates, spatial anisotropy is caused by the difference in density and orientation between the warp and fill directions of the glass yarn. This non-uniform structure means that electrical permittivity, thermal expansion and mechanical strength vary depending on whether they are measured along or across the board panel.
It affects both the electrical signal integrity and the dimensional stability of the circuit board during assembly.
Design Consequences
Signal propagation skew can develop between the two conductors of a high-speed differential pair if they are routed over different regions of the non-uniform glass weave, because they experience different effective dielectric constants. This difference in propagation speed can distort the differential signal, leading to increased jitter and signal degradation at multi-gigabit data rates. To mitigate this effect, layout designers often route critical high-speed traces at an angle to the glass weave, or utilize spread-glass fabrics that have a more uniform distribution of fibers.
These routing techniques distribute the glass fibers more evenly beneath the trace, which minimizes the directional variation in permittivity along the signal path.
Mechanical Stresses
Thermal expansion mismatches caused by this structural anisotropy can also lead to board warpage and twisting during the high-temperature solder reflow process. If the warp and fill directions of the laminate are not aligned correctly in the stackup, the resulting uneven stress can bend the board, which makes component placement difficult and causes solder joint defects. Fabricators monitor this alignment by using symmetric stackups and balancing the copper density across the panel.