Buildup HDI Stackup Design and Layer Thickness Control
Stackup thickness control requires calculating pressed prepreg heights over local copper patterns to hold impedance and microvia drilling tolerances.
Stacked Microvia Yield
Qualification Metric
Statistical percentage metrics measure the proportion of defect-free vertical interconnect chains surviving fabrication and assembly thermal stress cycles. Assessing stacked microvia yield evaluates the structural integrity of microvias placed directly on top of one another across sequential lamination layers. High yield rates confirm copper filling and laser drilling accuracy.
Failure Mechanism
Stacked microvias offer higher routing density than staggered microvias, but introduce cumulative thermal-mechanical stress at internal pad interfaces. Thermal expansion during reflow soldering exerts Z-axis tensile force along the stacked via barrel column. If copper plating inside lower microvia cavities contains voids or dimples, localized stress concentrations develop at the target pad interface.
Interfacial separation between the base of upper microvias and the target copper pad below leads to open circuits during thermal shock testing. Sequential lamination heat cycles further compound stress by repeatedly expanding substrate resin surrounding the stacked structure. Optimizing copper electroplating bath chemistry and laser ablation cleaning parameters improves interface adhesion, elevating cumulative yield metrics across complex HDI boards.
Process Verification
Interconnect stress testing and microsection inspection per IPC-TM-650 Method 2.6.27 quantify failure rates under accelerated thermal cycling. High-density designs mandate zero interfacial separation across test coupons to achieve Class 3 yield acceptance.