Expansion Differential
Thermal expansion variance between dissimilar materials joined in an electronic assembly generates mechanical shear forces during temperature changes. Thermal stress analysis accounts for substrate cte mismatch when evaluating mechanical compatibility between silicon die and organic laminates. Silicon chips exhibit low thermal expansion coefficients around three parts per million per degree Celsius, whereas FR-4 substrates expand at fifteen to seventeen parts per million.
Temperature fluctuations cause unequal dimensional changes across these joined layers, forcing interconnecting solder joints to absorb severe differential expansion.
Shear Stress
Thermal excursions force low-expansion silicon components and high-expansion organic circuit boards to expand at different rates across their shared plane. Solder joints located furthest from the component neutral point experience the highest distance-from-neutral-point deformation. Cyclic displacement induces severe shear strain inside perimeter solder interconnects, initiating micro-cracks near component pad interfaces.
Underfill encapsulation reduces shear stress by distributing mechanical forces across the entire component footprint rather than concentrating force on individual solder joints. Component geometry and board thickness dictate the total magnitude of shearing displacement. Repeated thermal cycling drives crack propagation through the solder matrix, increasing electrical resistance until open circuit failure occurs.
Substrate material selection utilizing low-expansion resins reduces thermal stress generation in high-reliability electronic assemblies.
Reliability Margin
Design guidelines mandate matching expansion coefficients of interposer materials to adjacent silicon structures within three parts per million per degree Celsius. Controlling expansion differences prevents premature solder joint fatigue in high-density packaging applications.
