Modeling Dynamic Parasitic Loading Effects on Scan Network Timing Margins
Dynamic parasitic extraction during ATPG shift prevents false timing violations by accounting for state-dependent capacitance and power rail collapses.
Transition Delay Faults
Defect Model
Manufacturing defects causing logic gates to switch slower than specified can prevent a circuit from operating at its target clock frequency. The category of transition delay faults includes slow-to-rise and slow-to-fall errors that are not detected by standard static logic tests. These faults are often caused by resistive bridges, weak transistors, metal voids, or excessive parasitic capacitance in the interconnects.
Fault Detection
Identification involves the use of specialized test patterns that measure the time taken for a signal to propagate through a logic path. During the screening for transition delay faults, the automated test equipment applies a stimulus at one clock edge and captures the response at the next, following a precise timing interval. This ensures that the circuit can handle transitions at the full operational speed required by the application.
Patterns are generated using sophisticated algorithms that target every potential transition in the design. By simulating the timing of these signals, engineers can differentiate between a slow gate and a catastrophic failure.
Quality Standard
Success in detecting these faults is measured by the transition delay fault coverage, which indicates the percentage of potential delay defects that the test suite can find. High coverage is necessary for products used in automotive or medical applications where timing failures can have serious consequences. The results of these tests are used to grade the components and to identify those that meet the highest performance standards.