Deriving Boundary Scan Diagnostic Coverage for High Density ASIC Arrays
Deriving boundary scan coverage for high-density ASIC arrays requires precise accounting of scannable versus un-scannable nets to prevent costly field escapes.
Un-Testable Net Liabilities
Quality Risk
Circuit nodes that cannot be reached by probes or verified through boundary scan represent a blind spot in the inspection process. Identifying these un-testable net liabilities allows a manufacturer to quantify the risk of shipping a defective product. These signals are often high-speed differential pairs or traces buried deep within a multilayer board without surface access.
Management Strategy
Each instance of a hidden connection must be reviewed by the design team to ensure the layout provides the best possible chance of a successful solder joint. Because these nets cannot be checked during electrical testing, they constitute un-testable net liabilities that might harbor latent faults like shorts or opens. Quality control teams often mitigate this by using automated x-ray inspection to view the connections beneath bga packages.
Statistical process control becomes more important for these features because there is no direct way to confirm their integrity on every unit. Designers may add redundant vias or increase pad sizes to improve the reliability of these critical paths. The total number of these nodes is a major factor in the final yield prediction.
Warranty Impact
A high volume of these inaccessible connections usually correlates with higher field failure rates. This necessitates a larger reserve fund for potential warranty repairs and replacements.