Verification Coverage
Electrical connectivity data derived from bare board design files represents the full set of intended circuit paths that require physical confirmation prior to assembly. Unprobed netlists identify specific nodes or traces that lack accessible test points for standard bed of nails or flying probe hardware. Engineers define these lists during the post layout phase to flag areas where signal paths reach internal layers or dense components without exposed copper pads.
Test technicians utilize these lists to modify fixture design or to incorporate alternative diagnostic procedures like boundary scan to reach the otherwise unreachable connections. Faults occurring within these segments remain hidden from traditional electrical continuity testing routines. Production teams must account for these gaps by implementing optical inspection or X-ray imaging to confirm structural integrity in the absence of electronic verification.
Diagnostic Constraint
Verification engineers calculate the percentage of unreachable nodes to determine the overall testability score of a complex printed circuit board assembly. A high density of hidden paths forces a transition from simple shorts testing to more elaborate structural analysis techniques. Component miniaturization often creates these scenarios as surface mount pads occupy the real estate previously dedicated to via access points.
Designers balance the need for miniaturization against the requirement for comprehensive electrical validation when they draft the layout geometry. When nodes remain inaccessible, the diagnostic software marks them as skipped, which leaves the manufacturer reliant on high quality manufacturing processes rather than post fabrication screening.
Acceptance Boundary
Quality managers categorize unprobed netlists as documentation that records the inherent limitations of a selected test strategy rather than as a report of a defective product. Fabrication facilities rely on these lists to determine if design changes allow for sufficient contact points before they commit to full production runs. If the assembly process fails to detect a defect in an unverified net, the resulting board carries a latent risk that standard field testing will not capture until a total signal failure occurs.
Final verification relies on the assumption that components soldered correctly to an unprobed trace will retain that connection throughout the service life of the hardware.
