IEEE Boundary Scan Architecture and Boundary Cell Selection Basics
Selecting boundary cells matching pin drive requirements enables full interconnect fault coverage and prevents system logic corruption during shift sequences.
Update Latch
Secondary Storage
Secondary storage registers situated parallel to boundary scan shift paths hold output values steady while new serial data shifts through scan chains. An update latch prevents transient signals from reaching system logic or component pins during shift operations. Data transfers into this latch only during explicit update execution phases.
Latch Decoupling
Boundary scan architecture relies on two-stage storage within each boundary cell to decouple internal serial shift sequences from physical component outputs. The update latch captures data held in the primary shift register on the falling edge of the test clock during the update-DR state. Keeping physical output pins stable during shift cycles prevents pin glitching, which would otherwise disrupt operating system states on adjacent integrated circuits.
During interconnect testing on populated printed circuit assemblies, output pins hold safe user-defined states until new test patterns are completely loaded across all boundary scan devices. Inadequate hold times or timing skew on update clock signals can cause incomplete latching, leaving output buffers in undefined or floating voltage states.
Pulse Width
Timing verification ensures that update clock pulse widths meet minimum vendor requirements across operating temperature ranges. Defective update latch operations result in unexpected output state shifts, producing false failure indications during board-level boundary scan testing.