Dielectric Insulation
Epoxy-based insulating sheets provide the necessary dielectric layers for high-density interconnect substrates. Use of ajinomoto build-up film enables the creation of fine-pitch circuitry on organic packages through a process of vacuum lamination and laser drilling. The material replaces traditional prepreg in high-end semiconductor packaging where wiring density requirements exceed the capabilities of standard glass-reinforced laminates.
Layer Addition
Sequential buildup processes rely on these films to form microvias that connect vertically across multiple thin layers. The ajinomoto build-up film undergoes a desmear process after drilling to ensure the copper plating adheres securely to the sidewalls. This chemical treatment creates a rough surface topography at the micron scale.
A permanent bond forms when the subsequent copper layer is deposited via electroless plating.
Performance Limit
Thermal expansion characteristics dictate the stability of the package during subsequent reflow cycles. While ajinomoto build-up film supports extremely small trace widths, its coefficient of thermal expansion must match the silicon die and the base laminate to prevent warping. Reliability hinges on the moisture absorption rates of the resin system.
Excess water intake during storage or processing leads to delamination when the assembly reaches peak soldering temperatures. Mechanical stress concentrates at the interface between the film and the core material under cyclic loading. Engineers monitor these stress points to prevent fatigue-driven cracking in the microvia structures.