Dielectric Breakdown
Uncoated circuit board screening evaluates raw dielectric integrity before components populate the layout. Bare substrate testing exposes internal copper planes and outer traces to high voltages to verify isolation resistance and catch opens or shorts before assembly starts. Manufacturers apply this electrical verification right after etching and solder mask application.
Electrical probes contact test pads across the panel according to netlists derived from computer aided design files. Voltage thresholds typically exceed standard operating limits to force insulation failure across marginal spacing before shipment to surface mount placement lines.
Impedance Margin
Signal speed requirements demand strict control over trace width and dielectric thickness during laminate pressing. Bare substrate testing measures capacitance and inductance values against specific trace geometries to confirm transmission line performance. Variations in glass weave density or resin content alter signal propagation speeds across high frequency boards.
Fabricators reject panels when characteristic impedance drifts outside calculated tolerances because downstream assembly cannot correct inherent dielectric anomalies.
Test Vector
Flying probe architectures navigate unpopulated circuit boards by moving independent mechanical arms across landing sites without dedicated fixture hardware. Fixtureless systems rely on software algorithms to generate optimal touch paths for high density boards with thousands of individual nets. Mechanical deflection of thin cores during probing risks damage to delicate surface finishes if contact force exceeds specified limits.
Netlist comparison software evaluates resistance measurements against predefined thresholds to isolate localized manufacturing defects before thermal stress introduces permanent failure.
