Boundary Scan Interconnect Testing Essentials for Populated Circuit Board Assemblies
Boundary scan interconnect testing turns silicon multiplexers into virtual probes to verify fine-pitch BGA solder joints without physical test pads.
Boundary Cell Architecture
Register Design
Silicon circuitry placed between the internal system logic and the physical device pins enables external testing of board-level connections. The use of boundary cell architecture provides a shift register stage next to each pin to capture and force logic levels. These electronic cells can isolate the internal logic of the chip to let the board-level scan path control the physical pin states.
This allows digital inputs and outputs to be tested without using external physical test probes.
Operational Mode
Control signals routed from the test access port switch the shift register stages between normal and test modes. In normal operation, signals pass directly through the cell with negligible propagation delay. During boundary-scan testing, the cell blocks the normal signal and shifts data through the boundary-scan register to set or read the pin status.
This mechanism provides full diagnostic access to high-density ball grid array packages where physical probe points are unavailable.
Defect Isolation
System software drives the cells on one chip to write logic states and reads the receiving cells on another chip to check the circuit path. Solder opens or bridges on a ball grid array are identified by the failure of the signal to propagate. This provides pin-level diagnostics.